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INTEGRATED CIRCUITS
PTN3500 Maintenance and control device
Product specification Supersedes data of 2000 Nov 22 2001 Jan 17
Philips Semiconductors
Philips Semiconductors
Product specification
Maintenance and control device
PTN3500
FEATURES
* I2C to parallel port expander * Internal 256x8 E2PROM * Self timed write cycle (5 ms typ.) * Four byte page write operation * Controlled pull-up on address lines * Low voltage VCC range of +2.5 V to +3.6 V * 5 V - tolerant I/Os * Low standby current (< 60 A ) * Power on Reset * Supports Live Insertion * Compatible with SMBus specification version 1.1 * High E2PROM endurance and data retention * Available in SO16 and TSSOP16 package options
DESCRIPTION
The PTN3500 is a general purpose maintenance and control device. It features an on-board E2PROM that can be used to store error codes or board manufacturing data for read-back by application software for diagnostic purposes. The eight quasi bidirectional data pins can be independently assigned as inputs or outputs to monitor board level status or activate indicator devices such as LEDs. The PTN3500 has three address pins allowing up to 8 devices to share the common two wire I2C software protocol serial data bus. The PTN3500 supports live insertion to facilitate usage in removable cards on backplane systems.
PIN CONFIGURATION
A0
1
16
VDD
A1 A2
2
15
SDA SCL
3 4 PTN3500
14 13
P0 P1 P2
WC P7 P6
5
12
6
11 10
P3 VSS
7 8
P5 P4
9
SW00541
Figure 1.
PIN DESCRIPTION
PIN NUMBER 1,2,3 4,5,6,7 8 9,10,11,12 13 14 15 16 SYMBOL A0:2 P0:3 VSS P4:7 WC SCL SDA VDD NAME AND FUNCTION Address Lines Quasi-bidirectional i/o pins Supply Ground Quasi-bidirectional i/o pins Write Control Pin. Should be tied LOW. I2C Serial Clock I2C Serial Data Supply Voltage
ORDERING INFORMATION
Type number n mber PTN3500D PTN3500DH Package Name SO16 TSSOP16 Description Plastic small-outline package; 16 leads; body width 7.5 mm Plastic thin shrink small-outline package; 16 leads; body width 4.4 mm Version SOT162-1 SOT403-1
FUNCTIONAL DIAGRAM
SCL SDA A2:0 I2C Control 8-Bit I/O Port
P7:0
WC
E2PROM 256 x 8
SW00562
Figure 2.
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853-2226 25435
Philips Semiconductors
Product specification
Maintenance and control device
PTN3500
CHARACTERISTICS OF THE I2C-BUS
The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy.
Start and stop conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the start condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the stop condition (P) (see Figure 4).
Bit transfer
One data bit is transferred during each clock phase. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals (See Figure 3).
System configuration
A device generating a message is a "transmitter", a device receiving is the "receiver". The device that controls the message is the "master" and the devices which are controlled by the master are the "slaves" (see Figure 5).
SDA
SCL
DATA LINE STABLE; DATA VALID
CHANGE OF DATA ALLOWED
SW00542
Figure 3. Bit transfer
SDA
SDA
SCL S START CONDITION P STOP CONDITION
SCL
SW00543
Figure 4. Definition of start and stop conditions
SDA SCL
MASTER TRANSMITTER/ RECEIVER
SLAVE RECEIVER
SLAVE TRANSMITTER/ RECEIVER
MASTER TRANSMITTER
MASTER TRANSMITTER/ RECEIVER
SW00544
Figure 5. System configuration
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Philips Semiconductors
Product specification
Maintenance and control device
PTN3500
Acknowledge (see Figure 6)
The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked
out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse, set-up and hold times must be taken into account. A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a stop condition.
DATA OUTPUT BY TRANSMITTER NOT ACKNOWLEDGE
DATA OUTPUT BY RECEIVER ACKNOWLEDGE
SCL FROM MASTER S START CONDITION
1
2
8
9
CLOCK PULSE FOR ACKNOWLEDGEMENT
SW00545
Figure 6. Acknowledgment on the I2C-bus
FUNCTIONAL DESCRIPTION
VDD WRITE PULSE 100 A DATA FROM SHIFT REGISTER D FF CI S POWER-ON RESET VSS P0 TO P7 Q
D FF READ PULSE CI S
Q
DATA TO SHIFT REGISTER
SW00546
Figure 7. Simplified schematic diagram of each I/O
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Philips Semiconductors
Product specification
Maintenance and control device
PTN3500
Addressing
For addressing, see Figure 8.
SLAVE ADDRESS SLAVE ADDRESS
S
0
1
0
0
A2
A1
A0
0
A
S
1
0
1
0
A2
A1
A0
0
A
(a) I/O EXPANDER (b) MEMORY
a.
b.
SW00547
Figure 8. PTN3500 slave addresses
Asynchronous Start
Following any Start condition on the bus, a minimum of 9 SCL clock cycles must be completed before a Stop condition can be issued. The device does not support a Stop or a repeated Start condition during this time period.
I/O OPERATIONS (see also Figure 7)
Each of the PTN3500's eight I/Os can be independently used as an input or output. Input I/O data is transferred from the port to the microcontroller by the READ mode (See Figure 10). Output data is transmitted to the port by the I/O WRITE mode (see Figure 9).
SCL
1
2
3
4
5
6
7
8
SLAVE ADDRESS (I/O EXPANDER)
DATA TO PORT
DATA TO PORT
SDA
S
0
1
0
0
A2
A1
A0
0
A
DATA 1
A
DATA 2
A
START CONDITION WRITE TO PORT
R/W
ACKNOWLEDGE FROM SLAVE
ACKNOWLEDGE FROM SLAVE
ACKNOWLEDGE FROM SLAVE
DATA OUT FROM PORT t pv
DATA 1 VALID t pv
DATA 2 VALID
SW00548
Figure 9. I/O WRITE mode (output)
SLAVE ADDRESS (I/O EXPANDER)
DATA FROM PORT
DATA FROM PORT
SDA
S
0
1
0
0
A2
A1
A0
1
A
DATA 1
A
DATA 4
1
P
START CONDITION READ FROM PORT
R/W
ACKNOWLEDGE FROM SLAVE
ACKNOWLEDGE FROM MASTER
STOP CONDITION
DATA INTO PORT
DATA 1 t ph
DATA 2
DATA 3 t ps
DATA 4
SW00549
Figure 10. I/O READ mode (input)
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Philips Semiconductors
Product specification
Maintenance and control device
PTN3500
Quasi-bidirectional I/Os (see Figure 11)
A quasi-bidirectional I/O can be used as an input or output without the use of a control signal for data direction. At power-on the I/Os are HIGH. In this mode, only a current source to VDD is active. An additional strong pull-up to VDD allows fast rising edges into heavily loaded outputs. These devices turn on when an output is written HIGH, and are switched off by the negative edge of SCL. The I/Os should be HIGH before being used as inputs.
SLAVE ADDRESS (PTN3500)
DATA TO PORT
DATA TO PORT
SDA
S
0
1
0
0
A2
A1
A0
0
A
1
A
0
A
P
START CONDITION
R/W
ACKNOWLEDGE FROM SLAVE
P3
ACKNOWLEDGE FROM SLAVE
P3
SCL
1
2
3
4
5
6
7
8
P3 OUTPUT VOLTAGE
P3 PULL-UP OUTPUT CURRENT
IOHt
IOH
SW00757
Figure 11. Transient pull-up current IOHt while P3 changes from LOW-to-HIGH and back to LOW
SYMBOL tpv tps tph
PARAMETER Output data valid; CL 100 pF Input data setup time; CL 100 pF Input data hold time; CL 100 pF
MIN
TYP
MAX 4
UNIT s s s
0 4
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Philips Semiconductors
Product specification
Maintenance and control device
PTN3500
MEMORY OPERATIONS Write operations
Write operations require an additional address field to indicate the memory address location to be written. The address field is eight bits long, providing access to any one of the 256 words of memory. There are two types of write operations, byte write and page write. Byte Write (see Figure 12) To perform a byte write the start condition is followed by the memory slave address and the R/W bit set to 0. The PTN3500 will respond with an acknowledge and then consider the next eight bits sent as the word address and the eight bits after the word address as the data. The PTN3500 will issue an acknowledge after the receipt of both the word address and the data. To terminate the data transfer
the master issues the stop condition, initiating the internal write cycle to the non-volatile memory. Only write and read operations to the Quasi-bidirectional I/O are allowed during the internal write cycle. Page Write (see Figure 13) A page write is initiated in the same way as the byte write. If after sending the first word of data, the stop condition is not received the PTN3500 considers subsequent words as data. After each data word the PTN3500 responds with an acknowledge and the two least significant bits of the memory address field are incremented. Should the master not send a stop condition after four data words the address counter will return to its initial value and overwrite the data previously written. After the receipt of the stop condition the inputs will behave as with the byte write during the internal write cycle.
SLAVE ADDRESS (MEMORY)
WORD ADDRESS
DATA
SDA
S 1 0 1 0 A2A1A0 0 A
A
AP
START CONDITION
R/W
ACKNOWLEDGE FROM SLAVE
ACKNOWLEDGE FROM SLAVE ACKNOWLEDGE FROM SLAVE
STOP CONDITION
SW00553
Figure 12. Byte write
SLAVE ADDRESS (MEMORY) SDA
WORD ADDRESS
DATA TO MEMORY
DATA TO MEMORY
S 1 0 1 0 A2 A1 A0 0 A R/W
A
DATA n
A
DATA +3n
AP
START CONDITION
ACKNOWLEDGE FROM SLAVE
ACKNOWLEDGE FROM SLAVE
ACKNOWLEDGE FROM SLAVE
STOP CONDITION
SW00554
Figure 13. Page Write
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Philips Semiconductors
Product specification
Maintenance and control device
PTN3500
Read operations
PTN3500 read operations are initiated in an identical manner to write operations with the exception that the memory slave address' R/W bit is set to a one. There are three types of read operations; current address, random and sequential. Current Address Read (see Figure 14) The PTN3500 contains an internal address counter that increments after each read or write access, as a result if the last word accessed was at address n then the address counter contains the address n+1. When the PTN3500 receives its memory slave address with the R/W bit set to one it issues an acknowledge and uses the next eight clocks to transmit the data contained at the address stored in the address counter. The master ceases the transmission by issuing the stop condition after the eighth bit. There is no ninth clock cycle for the acknowledge. Random Read (see Figure 15) The PTN3500's random read mode allows the address to be read from to be specified by the master. This is done by performing a dummy write to set the address counter to the location to be read.
The master must perform a byte write to the address location to be read, but instead of transmitting the data after receiving the acknowledge from the PTN3500 the master reissues the start condition and memory slave address with the R/W bit set to one. The PTN3500 will then transmit an acknowledge and use the next eight clock cycles to transmit the data contained in the addressed location. The master ceases the transmission by issuing the stop condition after the eighth bit, omitting the ninth clock cycle acknowledge. Sequential Read (see Figure 16) The PTN3500 sequential read is an extension of either the current address read or random read. If the master doesn't issue a stop condition after it has received the eighth data bit, but instead issues an acknowledge, the PTN3500 will increment the address counter and use the next eight cycles to transmit the data from that location. The master can continue this process to read the contents of the entire memory. Upon reaching address 255 the counter will return to address 0 and continue transmitting data until a stop condition is received. The master ceases the transmission by issuing the stop condition after the eighth bit, omitting the ninth clock cycle acknowledge.
SLAVE ADDRESS (MEMORY)
DATA FROM MEMORY
SDA
S 1 0 1 0 A2A1A0 1 A
P
START CONDITION
R/W ACKNOWLEDGE FROM SLAVE
STOP CONDITION
SW00556
Figure 14. Current Address Read
SLAVE ADDRESS (MEMORY) SDA
WORD ADDRESS
SLAVE ADDRESS (MEMORY)
DATA FROM MEMORY
S 1 0 1 0 A2 A1 A0 0 A R/W
A S 1 0 1 0 A2 A1 A0 1 A ACKNOWLEDGE FROM SLAVE R/W START CONDITION
P
START CONDITION
ACKNOWLEDGE FROM SLAVE
ACKNOWLEDGE FROM SLAVE
STOP CONDITION
SW00557
Figure 15. Random Read
SLAVE ADDRESS (MEMORY)
DATA FROM MEMORY
DATA FROM MEMORY
DATA FROM MEMORY
SDA
S 1 0 1 0 A2 A1 A0 1 A R/W
DATA n
A
DATA n+1
A
DATA N+X
P
START CONDITION
ACKNOWLEDGE FROM SLAVE
ACKNOWLEDGE FROM MASTER
ACKNOWLEDGE FROM MASTER
STOP CONDITION
SW00558
Figure 16. Sequential Read
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Philips Semiconductors
Product specification
Maintenance and control device
PTN3500
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. SYMBOL VCC VI II IO IDD ISS Ptot PO TSTG TAMB VESD Supply Voltage Input Voltage DC Input Current DC Output Current Supply Current Supply Current Total Power Dissipation Total Power Dissipation per Output Storage Temperature Operating Temperature Electrostatic Discharge: Human Body Model, 1.5 k, 100 pF Machine Model, 0 , 200 pF - - >2000 >200 V V -65 -40 PARAMETER -0.5 VSS - 0.5 -20 -25 -100 -100 MIN 4.0 5.5 20 25 100 100 400 100 +150 +85 MAX V V mA mA mA mA mW mW _C _C UNIT
DC ELECTRICAL CHARACTERISTICS
Tamb = -40_C to +85_C unless otherwise specified; VCC = 3.3 V SYMBOL Supply VDD IDDQ IDD1 IDD2 VPOR VIL VIH IOL IL CI VIL VIH IIHL(max) IOL IOH IOHt CI CO VIL VIH IL Supply Voltage Standby Current; A0, A1, A2, WC = HIGH Supply Current Read Supply Current Write Power on Reset Voltage Input LOW voltage Input HIGH voltage Output LOW current @ VOL = 0.4 V Input leakage current @ VI = VDD or VSS Input capacitance @ VI = VSS Input LOW voltage Input HIGH voltage Input current through protection diodes Output LOW current @ VOL = 1 V Output HIGH current @ VOH = Vss Transient pull-up current Input Capacitance Output Capacitance Input LOW voltage Input HIGH voltage Input leakage current @ VI = VDD Input leakage (pull-up) current @ VI = VSS -0.5 0.7 VDD -1 10 25 -0.5 0.7 VDD -400 10 30 25 100 2 10 10 0.3 VDD 5.5 1 100 300 -0.5 0.7 VDD 3 -1 1 7 0.3 VDD 5.5 400 2.5 3.3 3.6 60 1 2 2.4 0.3 VDD 5.5 V A mA mA V V V mA A pF V V A mA A mA pF pF V V A A PARAMETER MIN TYP MAX UNIT
Input SCL; input, output SDA
I/O Expander Port
Address Inputs (A0, A1, A2), WC input
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Philips Semiconductors
Product specification
Maintenance and control device
PTN3500
I2C-BUS TIMING CHARACTERISTICS
SYMBOL I2C-bus fSCL tSW tBUF tSU;STA tHD;STA tr tf tSU;DAT tHD;DAT tVD;DAT tSU;STO timing (see Figure 17; Note 1) SCL clock frequency tolerable spike width on bus bus free time START condition set-up time START condition hold time SCL and SDA rise time SCL and SDA fall time data set-up time data hold time SCL LOW to data out valid STOP condition set-up time - - 1.3 0.6 0.6 - - 250 0 - 0.6 - - - - - - - - - - - 400 50 - - - 0.3 0.3 - - 1.0 - kHz ns s s s s s ns ns s s PARAMETER MIN. TYP. MAX. UNIT
NOTE: 1. All the timing values are valid within the operating supply voltage and ambient temperature range and refer to VIL and VIH with an input voltage swing of VSS to VDD.
handbook, full pagewidth
PROTOCOL
START CONDITION (S)
BIT 7 MSB (A7)
BIT 6 (A6)
BIT 0 LSB (R/W)
ACKNOWLEDGE (A)
STOP CONDITION (P)
t
SU;STA
1 / f SCL
SCL
t
BUF
tr
t
f
SDA
t HD;STA
t
SU;DAT
t
HD;DAT
t
VD;DAT
MBD820
t SU;STO
SW00561
Figure 17.
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Philips Semiconductors
Product specification
Maintenance and control device
PTN3500
POWER-UP TIMING
SYMBOL tPUR
1
PARAMETER Power-up to Read Operation Power-up to Write Operation
MAX. 1 5
UNIT ms ms
tPUW1
NOTE: 1. tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. These parameters are guaranteed by design.
WRITE CYCLE LIMITS
SYMBOL tWR1 PARAMETER Write Cycle Time MIN. - TYP. (5) 5 MAX. 10 UNIT ms
NOTE: 1. tWR is the maximum time that the device requires to perform the internal write operation.
Write Cycle Timing
SCL
SDA
8th Bit Word n
ACK tWR Stop Condition Start Condition MEMORY ADDRESS
SW00560
Figure 18.
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Philips Semiconductors
Product specification
Maintenance and control device
PTN3500
SOLDERING Introduction
There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our IC Package Databook (order code 9398 652 90011). seconds depending on heating method. Typical reflow temperatures range from 215 to 250C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45C. Wave soldering Wave soldering is not recommended for SSOP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. If wave soldering cannot be avoided, the following conditions must be observed: followed by a smooth laminar wave) soldering technique should be used.
DIP
Soldering by dipping or by wave The maximum permissible temperature of the solder is 260C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. Repairing soldered joints Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400C, contact may be up to 5 seconds.
* A double-wave (a turbulent wave with high upward pressure * The longitudinal axis of the package footprint must be
parallel to the solder flow and must incorporate solder thieves at the downstream end. Even with these conditions, only consider wave soldering SSOP packages that have a body width of 4.4 mm, that is SSOP16 (SOT369-1) or SSOP20 (SOT266-1). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150C within 6 seconds. Typical dwell time is 4 seconds at 250C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Repairing soldered joints Fix the component by first soldering two diagonally opposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320C.
SO and SSOP
Reflow soldering Reflow soldering techniques are suitable for all SO and SSOP packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300
PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specifications defined by Philips. This specification can be ordered using the code 9398 393 40011.
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Philips Semiconductors
Product specification
Maintenance and control device
PTN3500
SO16: plastic small outline package; 16 leads; body width 7.5 mm
SOT162-1
2001 Jan 17
13
Philips Semiconductors
Product specification
Maintenance and control device
PTN3500
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
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14
Philips Semiconductors
Product specification
Maintenance and control device
PTN3500
Data sheet status
Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 2001 All rights reserved. Printed in U.S.A. Date of release: 01-01 Document order number: 9397 750 07932
Philips Semiconductors
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